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PRELIMINARY DATA SHEET
MICRONAS
MAD 4868A Micronas Audio Delay
Edition May 11, 2004 6251-636-1PD
MICRONAS
MAD 4868A
Contents Page 3 3 3 3 5 5 5 6 6 7 7 7 7 7 8 8 9 9 9 12 12 13 13 14 14 15 15 16 16 17 17 17 17 18 19 22 24 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 3. 3.1. 3.1.1. 3.1.2. 3.2. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 5. 6. Title Introduction Features Interfaces Miscellaneous Functional Description Block Diagram I2S Bus Interface Serial Mode - One Data Line Parallel Mode - Four Data Lines Delay Line Word Width Output Data Mute Reset RAM Clear Control Interface I2C Bus Interface Protocol Description Start-Up Sequence: Power-Up and I2C-Controlling Description of User Interface Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Appendix A: Application Diagram (Exemplary) Data Sheet History
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Micronas Audio Delay
1.2. Interfaces - 8-channel Micronas I2S input and output: In combination with Micronas ICs (serial mode) (e.g. MSP 44/46xyK, MAS 35xyH), eight audio channels can be routed through MAD 4868A by using four lines only. - 4x2-channel standard I2S inputs and outputs (parallel mode) allow routing eight audio channels with sampling rates of 4...192 kHz through MAD 4868A - I2C control for delay time programming - Address select to set one out of two available I2C addresses
1. Introduction The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and consumer audio applications. The IC is designed for synchronizing audio and video signals ensuring "Lip Sync" by delaying the audio signal with the same amount of time as the video signal is delayed in a TV's video processing. For TV designs, independent signals for loudspeakers, headphones, and line-out or S/PDIF out must be provided, resulting in the need to delay six independent audio channels. Especially modern flat panel TVs (LCD- or plasmaTVs) require "Lip Sync" because of their video deinterlacing, processing, scaling, and pixel-oriented display. In battery-operated "wireless TVs" using digital transmission, the compression/decompression also may delay video more than audio. Therefore, additional audio delay is necessary. Consumer audio applications such as A/V-Receivers or HTiB can also use MAD 4868A to offer "Lip Sync" as an additional feature to delay audio according to the video delay appearing in the TV, beamer, or monitor used in a home cinema setup. The MAD 4868A is equipped with all interfaces, as well as embedded RAM. This makes the IC easy to use and avoids RAM availability and pricing problems. In its PMQFP44-1 package with 0.8 mm pitch, the MAD 4868A requires only little PCB space but is suitable for wave soldering and reflow soldering.
1.3. Miscellaneous - No crystal required: The MAD 4868A derives all internal clocks from the I2S clock. - Very few external components required - 5 V or 3.3 V single supply voltage - Very low power consumption - 5 kHz to 192 kHz sampling rates - Cascadable, extendable: Two MAD 4868As can be cascaded to extend the delay time, either in 8-channel (serial) mode using one data line or in 2-channel (parallel) mode using up to four data lines.
1.1. Features - 32 k audio samples RAM: Total delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate - 32/18-bit word width: 32-bit High-Resolution mode or 18-bit Standard mode - Sampling rates from 32 kHz to 48 kHz for serial 8-channel mode are supported - Sampling rates from 4 kHz to 192 kHz for parallel 2-channel mode are supported - Memory allocation: MAD 4868A's memory can be allocated for 1...8 audio channels. Delay time can be programmed for each channel individually.
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IN
INPUT BUFFER
t1
t2
t3
t4
t5 t6 t7
t8
OUTPUT BUFFER
OUT
RAM
I2C
CONTROL
MAD 4868A
Fig. 1-1: Block diagram of the MAD 4868A
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2. Functional Description 2.1. Block Diagram In Fig. 2-1, a simplified block diagram of the IC is given. Between 1 and 8 channels can be delayed individually by a programmable number of samples nx. The delay RAM offers, depending on the accumulated adjusted delay, a word width of 32 or 18 bits. The accumulated delay must not exceed 7FF0hex (32752dec) samples (i.e. 682 ms @ 48 kHz Fs). As the bit clock (I2S_DEL_CL) is limited to 12.288 MHz and the used I2S bus format has a fixed word length of 32 bit, the maximum sample rate fs is 192 kHz in parallel mode (2-channels per data line) and 48 kHz in serial mode (8-channels on I2S_DEL_IN1/OUT1).
2.2. I2S Bus Interface The MAD 4868A has four I2S data input lines and four I2S data output lines which together with I2S_DEL_WS and I2S_DEL_CL form one I2S bus interface for various sample rates in serial (8-channel) or parallel (2channel) mode. The I2S_DEL_CL, I2S_DEL_WS, and I2S_DEL_IN1...4 are inputs to the MAD 4868A (tristate) while I2S_DEL_OUT1...4 are outputs. Bit[1:0] of the CONTROL register set the output driver active or tristate and its strength to weak or strong (see Table 3-3 on page 10). The interface works only in synchronous slave mode and with a fixed wordlength of each audio sample of 32 bits. Two different operational modes can be adjusted as described in the following sections.
Frame Clock (WS)
0ms
Input Buffers D1 D2 Demultiplexer D3 D4 D5 D6 D7 D8 2..8 DI
[t1]
Output Buffers D1 Multiplexer / Mute D2 D3
[t2]
[t3] [t4] [t5] [t6] [t7] [t8] not used
680ms@48kHz
D4 D5 D6 D7 D8
2..8 DO
CONTROL[1:0]
Output Driver Active Output Driver Strength
CONTROL[9:2]
Output Data Mute
Fig. 2-1: Simplified block diagram of the MAD 4868A
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2.2.1. Serial Mode - One Data Line The MAD 4868A is capable of receiving signals with up to eight audio samples in a fixed 8-channel I2S format on one data line (serial mode). The interface consists of the pins: - I2S_DEL_IN1: I2S data input, with 8 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample - I2S_DEL_OUT1: I2S data output, with 8 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample - I2S_DEL_CL: I2S clock - I2S_DEL_WS: I2S word strobe signal defines the frame start at the sample rate. As the bit clock must not exceed 12.288 MHz, the maximum sample rate is limited to 48 kHz when the MAD 4868A is operated in this mode. This mode is used for the connection to the Delay Line Interface of the MSP 44/46xyK. In serial mode, the number of audio channels must be even and less or equal eight. A timing diagram is shown in Fig. 4-8 on page 21. In this mode, it is possible to mute each output channel individually by means of the CONTROL register bit[2:9.]
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2.2.2. Parallel Mode - Four Data Lines The MAD 4868A is capable of receiving stereo signals on up to four I2S data lines in Parallel Mode with a total of up to eight audio channels. The interface consists of the pins: - I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4: I2S data input with 2 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample - I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4: I2S data output with 2 audio channels per I2S_DEL_WS cycle and 32 bit per audio sample - I2S_DEL_CL: I2S clock - I2S_DEL_WS: I2S word strobe signal defines the left and right sample at the sample rate. As the bit clock must not exceed 12.288 MHz, the sample rate can be a maximum of 192 kHz when MAD 4868A is operated in this mode. This mode is used for connection to e.g. the I2S interface of the Micronas MSP 34/44xyG or any other audio DSP.
Note: DVSUP2 drives the pins DA_IN_2...4 and DA_OUT_2...4. To avoid radiation from not connected pins, it is recommended not to connect DVSUP2 when MAD 4868A is to be used in Serial Mode.
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2.3. Delay Line The MAD 4868A has a delay line of 32k Words of RAM built in. The RAM can be split up into portions of different length to delay between 1 and 8 channels of audio. This makes the MAD 4868A very flexible. All channels can be delayed individually. The maximum amount of adjusted delay must not exceed 7FF0hex (32752dec) samples. Equipped with a pointer unit and programmed with variable pointer offsets for the delay channels 1 to 8, the programming of the individual delay times is realized by means of its own control register for each delay channel (see Table 3-3 on page 10). The delay time depends on the used sample frequency on the I2S-bus. Since, not the delay time, but the number of delayed samples is programmed, the corresponding number of samples is calculated using the follwing formula:
2.4. Word Width The audio sample word width inside the RAM of the MAD 4868A depends on the adjusted number of samples for the delay. MAD 4868A automatically switches the word width to 32 bit if the total delay length is below 3FF8hex (16376dec) i.e. half of the maximum length. Otherwise, the delay line is 18 bit wide. By means of bit[14] of the CONTROL register, a read out value is available in parallel mode which indicates the internally adjusted word width.
2.5. Output Data Mute The output data channel 1-8 can be muted by means of the CONTROL register bit[2:9]. In serial mode, each output data channel can be muted individually, while in parallel mode, all channels 1-8 have to be adjusted individually to the same value. It is recommended to mute the output data channels during the power-up sequence of the MAD 4868A, as well as during readjustment of the delay time during normal operation. To avoid any audible disturbances, the minimum mute time must be at least the maximum programmed delay time of all channels.
n x = ( t ms ( x ) x f s ) - 1
nx = number of samples tms = time in milliseconds fs = sample rate
2.6. Reset The Reset is active low and resets the I2S and I2Cinterfaces of the MAD 4868A. Since there is no RAM clear facility, the output of the MAD 4868A after reset is random, as long as no valid samples have been inserted and passed the delay line (e.g. after Reset, enable the I2S bus output but keep Mute active until the maximum programmed delay time is passed).
In the pointer unit, the offsets are used as increments for the address pointer to receive the correct RAM address of the delayed sound samples.
Note: Reprogramming the delay length of a channel affects the output of the channels with higher numbers. Due to the "linked list" principle of the RAM organisation, the upper channels read from "wrong memory" until it is filled up with new audio samples. Therefore, it is recommended to mute the output of the delay line for the max programmed delay time of all channels.
2.7. RAM Clear A RAM Clear can be performed manually. It is recommended to apply a manual RAM Clear after the powerup of the MAD 4868A. Mute the output data channel 18, apply a digital zero signal on all used channels. This can be achieved, for example, by selecting an I2S input with a prescaler setting to Mute in the MSP 44/ 46xyK for all used MAD 4868A input channels. The digital zero signal must be applied for at least the maximum programmed delay time of all channels.
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3. Control Interface 3.1. I2C Bus Interface The MAD 4868A is controlled via its I2C bus slave interface. The IC is selected by transmitting an MAD 4868A device address. In order to allow two MAD 4868A ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high or low, the MAD 4868A responds to different device addresses. A device address pair is defined as a write address and a read address.
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Writing is done by sending the write device address, followed by the subaddress byte and the data bytes. Reading is done by sending the write device address, followed by the subaddress byte. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. See Table 3-1 for a list of available device addresses. See Table 3-2 for a list of available subaddresses. A general timing diagram of the I2C bus is shown in Fig. 3-1 on page 9.
Table 3-1: I2C Bus Device Addresses
ADR_SEL Mode MAD 4868A device address Write 82hex Low (connected to DVSS) Read 83hex Write 84hex High (connected to DVSUP) Read 85hex
Table 3-2: I2C Bus Subaddresses
Name CONTROL CH1_DELAY CH2_DELAY CH3_DELAY CH4_DELAY CH5_DELAY CH6_DELAY CH7_DELAY CH8_DELAY Binary Value 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 Hex Value 00 01 02 03 04 05 06 07 08 Mode Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Function Write: Interface control Read: Status delay channel 1 delay channel 2 delay channel 3 delay channel 4 delay channel 5 delay channel 6 delay channel 7 delay channel 8
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3.1.1. Protocol Description Write to CONTROL and CHX_DELAY Registers
S write device address Wait ACK sub-addr ACK data-byte ACK data-byte ACK P high low
Read from CONTROL or CHX_DELAY Register
S write device address Wait ACK sub-addr ACK S read device address Wait ACK data-byte- ACK data-byte NAK P high low
Note: S = P= ACK = NAK =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on SDA from slave (= MAD, light gray) or master (= controller, dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate `End of Read' or from MAD indicating internal error state Wait = I2C-Clock line is held low, while the MAD is processing the I2C command. This waiting time is max. 1 ms
SDA S SCL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.2. Start-Up Sequence: Power-Up and I2C-Controlling After POWER-ON or RESET, the IC is in an inactive state. All registers are in their Reset position (see Table 3-3 on page 10), the Output Driver is set to tristate. The controller has to initialize the CONTROL and CHX_DELAY registers.
3.2. Description of User Interface Write and read registers are 16 bit wide, whereby the MSB is denoted bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All registers are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be accessed.
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Table 3-3: User Interface Sub Address (hex) 00hex Function Mode
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Reset Value (hex) 0000hex
Name
Control bit[15] bit[14]1) must be ignored HighRes Flag (word width of delayed samples) 0 18 bit 1 32 bit (high resolution)
CONTROL
bit[13:11] not used, must be set to 0 bit[10] WS_POL (word strobe polarity) 0 WS_POL = Low-High marks Framestart e.g. MSP 44/46xyK I2S-5 Interface, all MSPs 8-channel mode 1 WS_POL = High-Low marks Framestart e.g. MSP I2S_OUT (2-channel mode) Output Data Mute channel 8 Output Data Mute channel 7 Output Data Mute channel 6 Output Data Mute channel 5 Output Data Mute channel 4 Output Data Mute channel 3 Output Data Mute channel 2 Output Data Mute channel 1 0 muted 1 0 dB Output Data Mute channel 1-8 can be set individually in serial mode, in parallel mode, Output Data Mute channel 1-8 must all be set to the same value. Output Driver Active 0 tristate 1 active Output Driver Strength 0 weak 1 strong
bit[9] bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2]
bit[1]
bit[0]
1)
bit[14] is read only
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Table 3-3: User Interface, continued Sub Address (hex) 01hex... 08hex Function Mode Reset Value (hex) 0000hex Name
Channel Delay The delay time tms in milliseconds; Delay nx must be calculated and set as number of samples: nx = (tms(x) x fs) -1 bit[15:0] example: samples: min delay nx x = 1..8; n = 0..32752 number of delayed samples for channel x, x = 1...8 fs = 32 kHz 31 s 1.00 ms 1.50 ms 3.00 ms 1023 ms fs = 48 kHz 21 s 0.66 ms 1.00 ms 2.00 ms 682 ms fs = 96 kHz 10 s 0.33 ms 0.50 ms 1.00 ms 341 ms fs = 192 kHz 5 s 0.16 ms 0.25 ms 0.50 ms 170 ms
CH1_DELAY CH2_DELAY CH3_DELAY CH4_DELAY CH5_DELAY CH6_DELAY CH7_DELAY CH8_DELAY
nx 0 1Fhex 2Fhex 5Fhex ... max delay1) 7FF0hex
1) Since there are 32 KWords of RAM accessible, the SUM(n1:n8) must be less than 7FF0hex (e.g. in total a maximum delay of 682 ms at a 48 kHz sample rate must not be exceeded).
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4. Specifications 4.1. Outline Dimensions
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Fig. 4-1: PMQFP44-1: Plastic Metric Quad Flat Package, 44 leads, 10 x 10 x 2 mm3 Ordering code: QG Weight approximately 0.5 g
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4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant OBL = obligatory; connect as described in circuit diagram
Pin No.
PMQFP44-1
Pin Name
Type
Connection
(If not used)
Short Description
1...12 13 14 15 16 17 18 19 20 21...33 34 35 36 37 38 39 40 41 42 43 44
NC I2S_DEL_OUT2 I2S_DEL_OUT3 I2S_DEL_OUT4 DVSUP2 DVSS2 I2S_DEL_IN2 I2S_DEL_IN3 I2S_DEL_IN4 NC RESETQ TEST DVSS1 DVSUP1 I2S_DEL_WS I2S_DEL_CL I2S_DEL_IN1 I2S_DEL_OUT1 ADR_SEL I2C_DA I2C_CL IN IN SUP SUP IN IN IN OUT IN IN/OUT IN/OUT OUT OUT OUT SUP SUP IN IN IN
LV OBL OBL OBL DVSUP DVSS OBL OBL OBL LV OBL DVSS DVSS DVSUP OBL OBL OBL OBL OBL OBL OBL
Not Connected I2S data output channel 3 + 4 I2S data output channel 5 + 6 I2S data output channel 7 + 8 Digital Power Supply Digital Ground I2S data input channel 3 + 4 I2S data input channel 5 + 6 I2S data input channel 7 + 8 Not Connected Power-On Reset (active low) Test pin Digital Ground Digital Power Supply I2S word strobe input I2S clock input I2S data input channel 1 + 2 or 1..8 I2S data output channel 1 + 2 or 1..8 I2C bus address select I2C Data I2C Clock
4.3. Pin Descriptions I2C_CL - I2C Clock Input/Output (Fig. 4-3) Via this pin, the I2C-bus clock signal has to be supplied. I2C_DA - I2C Data Input/Output (Fig. 4-3) Via this pin, the I2C-bus data is written to or read. I2S_DEL_WS - Word Strobe Input (Fig. 4-4) Word strobe line for the I2S bus. An external word strobe has to be supplied. I2S_DEL_CL - Clock Input (Fig. 4-4) Clock line for the I2S bus. An external clock has to be supplied.
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I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4 - Data Input (Fig. 4-4) Input of I2S data. I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 - Data Output (Fig. 4-5) Output of I2S bus. DVSUP1, DVSUP2 - Digital Supply Voltage Power supply must be connected to +5 V or +3.3 V power supply. DVSS1, DVSS2 - Digital Ground Ground connection. TEST - This pin enables factory test modes. For normal operation, it must be connected to DVSS RESETQ - Reset Input (Fig. 4-4) In the steady state, high level is required. A low level resets the interfaces of MAD 4868A. ADR_SEL - I2C Bus Address Select (Fig. 4-4) By means of this pin, one of two device addresses can be selected. The pin can be connected to DVSS (I2C device addresses 82/83hex) or to DVSUP (84/85hex). NC - Pin not connected 4.5. Pin Circuits
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N GND Fig. 4-3: Input/Output Pins: I2C_CL, I2C_DA
DVSUP P N GND Fig. 4-4: Input Pins:I2S_DEL_CL, I2S_DEL_WS, I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4, ADR_SEL, RESETQ
DVSUP P N
4.4. Pin Configuration
NC NC NC NC NC NC NC NC NC NC NC
GND Fig. 4-5: Output Pins: I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4
33 32 31 30 29 28 27 26 25 24 23 RESETQ TEST DVSS1 DVSUP1 I2S_DEL_WS I2S_DEL_CL I2S_DEL_IN1 I2S_DEL_OUT1 ADR_SEL I2C_DA I2C_CL 34 35 36 37 38 39 40 41 42 43 44 1 NC NC NC NC NC NC NC NC NC NC 2 3 4 5 6 7 8 9 10 11 NC 22 21 20 19 18 NC NC I2S_DEL_IN4 I2S_DEL_IN3 I2S_DEL_IN2 DVSS2 DVSUP2 I2S_DEL_OUT4 I2S_DEL_OUT3 I2S_DEL_OUT2 NC
MAD 4868A
17 16 15 14 13 12
Fig. 4-2: PMQFP44-1 package
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4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (VSS = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min. TA1) TC TS PMAX VSUP VIdig IIdig
1)
Limit Values Max. 70 95 125 860
Unit
Ambient Temperature Case Temperature Storage Temperature Maximum Power Dissipation Supply Voltage Input Voltage, all Digital Inputs Input Current, all Digital Pins
- - -
-10 -10 -40
C C C mW V V mA
DVSUP1, DVSUP2
-0.3 -0.3
6.0 VSUP2+0.3 +20
-
-20
Measured on standard board according to JESD 51 Standard with maximum power consumption allowed for this package.
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4.6.2. Recommended Operating Conditions
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Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSS = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in Section 4.6.3.3. of this document.
4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. TA TC PMAX VSUP Ambient Operating Temperature Case Operating Temperature Maximum Power Dissipation Supply Voltage DVSUP1, DVSUP2 3.0 - - 0 0 Limit Values Typ. Max. 70 70 50 5.25 C C mW V Unit
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4.6.3. Characteristics For Min./Max. values: at TA = 0 to 70 C VSUP = 3.15 to 3.45 V if VSUP = 3.3 V VSUP = 4.75 to 5.25 V if VSUP = 5 V at TA = 60 C VSUP = 3.3 V or VSUP = 5 V
For typical values:
4.6.3.1. General Characteristics
Symbol Parameter Pin Name Min. Supply ISUP Supply Current (active) (VSUP = 5 V) Supply Current (active) (VSUP = 3.3 V) DVSUP1, DVSUP2 2.4 2.9 0.8 1.15 1.5 0.5 mA mA mA mA mA mA Serial mode fs = 48 kHz Parallel mode fs 192 kHz Parallel mode fs 48 kHz Serial mode fs = 48 kHz Parallel mode fs 192 kHz Parallel mode fs 48 kHz Limit Values Typ. Max. Unit Test Conditions
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Pin Name Min. Digital Input Levels VDIGIL VDIGIH ZDIGI Digital Input Low Voltage Digital Input High Voltage Input Capacitance ADR_SEL 0.5 5 0.2 VSUP VSUP pF Limit Values Typ. Max. Unit Test Conditions
4.6.3.3. Reset Input and Power-Up
Symbol Parameter Pin Name Min. RESETQ Input Levels VRHL VRLH ZRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Capacitance RESETQ 0.5 5 0.2 VSUP VSUP pF Limit Values Typ. Max. Unit Test Conditions
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4.6.3.4. I2C-Bus Characteristics
Symbol Parameter Pin Name Min. VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 I2C-Bus Input Low Voltage I2C-Bus Input High Voltage I2C Start Condition Setup Time I C Stop Condition Setup Time I2C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-BUS Frequency I2C-Data Output Low Voltage I2C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock SCL, SDA SCL
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Limit Values Typ. Max. 0.3 0.6 120 120 55 55 500 500 1.0 0.4 1.0 15 100
Unit
Test Conditions
SCL, SDA
VSUP VSUP ns ns ns ns ns ns MHz V A ns ns fI2C = 1 MHz II2COL = 3 mA VI2COH = 5 V
1/FI2C SCL TI2C4 TI2C3
TI2C1 SDA as input
TI2C5
TI2C6
TI2C2
TI2COL2 SDA as output
TI2COL1
Fig. 4-6: I2C bus timing diagram
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4.6.3.5. I2S-Bus Characteristics
Symbol VIL VIH ZI ILEAK VOL VOH Parameter Input Low Voltage Input High Voltage Input Impedance Input Leakage Current Output Low Voltage Output High Voltage I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 Pin Name I2S_DEL_CL I2S_DEL_WS I2S_DEL_IN1 I2S_DEL_IN2 I2S_DEL_IN3 I2S_DEL_IN4 Min. Typ. Max. 0.2 0.5 5 -1 1 0.4 VSUP - 0.3 Unit VSUP VSUP pF A V V 0 V < UINPUT< DVSUP IOL = 1 mA IOH = -1 mA Test Conditions
I2S Interface Parallel Mode 2-channel ts_I2SDEL Input Setup Time before Rising Edge of Clock Input Hold Time after Rising Edge of Clock Output Delay Time after Falling Edge of Clock I2S_DEL_CL I2S_DEL_IN1, I2S_DEL_IN2, I2S_DEL_IN3, I2S_DEL_IN4 7 ns for details see Fig. 4-8 "I2S bus timing diagram, serial mode (8-channel)"
th_I2SDEL td_I2SDEL
10 15
ns ns CL=30 pF
I2S_DEL_OUT1, I2S_DEL_OUT2, I2S_DEL_OUT3, I2S_DEL_OUT4 WS CL 4 0.256 0.9
fI2SDEL_WS fI2SDEL_CL RCL
Word Strobe Input Frequency Clock Input Frequency Clock Input Ratio
192 12.288 1.1
kHz MHz
deviation = 300 ppm deviation = 300 ppm
I2S Interface Serial Mode 8-channel ts_I2SDEL Input Setup Time before Rising Edge of Clock Input Hold Time after Rising Edge of Clock Output Delay Time after Falling Edge of Clock Word Strobe Input Frequency Clock Input Frequency Clock Input Ratio I2S_DEL_OUT1, I2S_DEL_WS I2S_DEL_CL 4 1.024 0.9 I2S_DEL_CL I2S_DEL_WS I2S_DEL_IN1 7 ns for details see Fig. 4-8 "I2S bus timing diagram, serial mode (8-channel)"
th_I2SDEL td_I2SDEL fI2SDEL_WS fI2SDEL_CL RCL
10 15 48 12.288 1.1
ns ns kHz MHz CL=30 pF
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May 11, 2004; 6251-636-1PD
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MAD 4868A
PRELIMINARY DATA SHEET
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1/FI2SDEL_WS I2S_DEL_WS(if Control[10] = 0)
I2S_DEL_WS(if Control[10] = 1)
Detail C
I2S_DEL_CL Detail A I2S_DEL_INx
LSBr MSBl LSBl MSBr LSBr MSBl
channel xleft with 32 bits Detail B I2S_DEL_OUTx
LSBr MSBl LSBl MSBr
channel xright with 32 bits
LSBr
MSBl
channel xleft with 32 bits
channel xright with 32 bits
Detail A,B,C
td_I2SDEL I2S_DEL_WS
I2S_DEL_CL
ts_I2SDEL I2S_DEL_INx
th_I2SDEL
td_I2SDEL
I2S_DEL_OUTx
Fig. 4-7: I2S bus timing diagram, parallel mode (2-channel)
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May 11, 2004; 6251-636-1PD
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MAD 4868A
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1/FI2SDEL_WS I2S_DEL_WS(if Control[10] = 0)
Frame Start will be identified if I2S_DEL_WS is high for at least two clock cycles
I2S_DEL_WS(if Control[10] = 1) I2S_DEL_CL Detail A I2S_DEL_IN1
LSB8 MSB1
Frame Start will be identified if I2S_DEL_WS is low for at least two clock cycles
LSB1
MSB2
LSB4
MSB4
LSB8
MSB1
4 channels with 32 bits
4 channels with 32 bits
I2S_DEL_OUT1
LSB8
MSB1
LSB1 MSB2
LSB4
MSB5
LSB8 MSB1
4 channels with 32 bits
4 channels with 32 bits
Detail A
td_I2SDEL I2S_DEL_WS
I2S_DEL_CL
ts_I2SDEL I2S_DEL_IN1
th_I2SDEL
td_I2SDEL
I2S_DEL_OUT1
Fig. 4-8: I2S bus timing diagram, serial mode (8-channel)
Micronas
May 11, 2004; 6251-636-1PD
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80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
+
11 10 9 8 7 6 5 4 3 2 1
STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 SPDIF_OUT NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_INANA_IN1+ AVSUP AVSUP
NC NC NC NC NC NC NC NC NC NC NC
12 13 14 15 16 17 18 19 20 21 22
470n
MAD4868A
NC NC NC NC NC NC NC NC NC NC NC
23 24 25 26 27 28 29 30 31 32 33
GND
1n
1n
1n
1n
1n
1n
1n
1n
DACA_L VREF2 DACM_R DACM_L DACM_C DACM_SUB DACM_SR DACM_SL SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL-M
1n5
GND
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SC2outR SC2outL
SC1outR
SC1outL
SC2outR
SC2outL
SC3outR
SC3outL
SC1inL
SC1inR
SC2inL
SC2inR
SC3inL
SC3inR
SC4inL
SC1outR SC1outL
to AMP to AMP to AMP to AMP to AMP to AMP to AMP to AMP
10u/16V
SC4inR
SC5inL
+
22u/16V 22u/16V 100R 100R 100R 100R 22u/16V 22u/16V
+
+
+
+
+
22u/16V 22u/16V
100R 100R
330p 330p
330p 330p 470R 470R 470R 470R
330p 330p 470R 470R
330p 330p 470R 470R
330p 330p 470R 470R
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1M
1M
1M
1M
1M
1M
PRELIMINARY DATA SHEET
Micronas
GND
GND
GND
GND
GND
GND
GND
GND
SC5inR
+
+
GND
10u/16V
+
22
+5V 10R 100n
3p3 18.432MHz 3p3
RESETQ from ResetCircuit BC847 GND
1k
GND
GND
SDA from/to C
SCL from C
SPDIFout
56p
100n 100n
56p
180R
1k
3k3
from IF
GND GND
56p
MAD 4868A
GND
from IF
GND
GND
from IF
+
2u2
+5V GND
470p 1n5 10u/16V 10u/16V 100n
GND GND
470n SC5inR SC5inL SC1inR SC1inL
GND
5. Appendix A: Application Diagram (Exemplary)
GND
470n SC2inR SC2inL
+5V
2u2
+5V
NC I2S_DEL_OUT2 I2S_DEL_OUT3 I2S_DEL_OUT4 DVSUP DVSS I2S_DEL_IN2 I2S_DEL_IN3 I2S_DEL_IN4 NC NC
I2C_CL I2C_DA ADR_SEL I2S_DEL_OUT1 I2S_DEL_IN1 I2S_DEL_CL I2S_DEL_WS DVSUP DVSS TEST RESETQ
44 43 42 GND 41 40 39 38 10n 10 22 37 36 35 GND 34
+
1n5 470p 220p
MSP 44xyK
GND
470n SC3inR SC3inL
GND
10u/16V
GND
470n SC4inR SC4inL 100n
100n
GND
+ 3u3/16V
GND
SC3outL SC3outR 470p
100n
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 I2S_DEL_IN I2S_DEL_OUT I2S_DEL_CL I2S_DEL_WS DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2 NC I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 I2S_DA_IN4 DACA_R NC NC AVSS AVSS SC5_IN_R SC5_IN_L VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS SC3_OUT_L SC3_OUT_R
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
May 11, 2004; 6251-636-1PD
GND GND GND GND GND GND GND GND
10u/16V 100u
+8V
PRELIMINARY DATA SHEET
MAD 4868A
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Micronas
May 11, 2004; 6251-636-1PD
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MAD 4868A
6. Data Sheet History 1. Preliminary Data Sheet: "MAD 4868A Micronas Audio Delay", May 11, 2004, 6251-636-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
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Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-636-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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May 11, 2004; 6251-636-1PD
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